Three phase alternating current (AC) power converters have numerous applications, such as motor control, solar inverters, wind energy and uninterruptible power supplies (UPS). FIG. 1 identifies a conventional circuit topology based on six transistors with antiparallel diodes in the power stage (15). The six transistors are independently turned on and off based on six pulse width modulated (PWM) signals generated by a controller (10). Modern implementations make use of a microprocessor or gate array to directly control the power stage switching. In conventional implementations, digital waveform synthesis makes use of a phase accumulator (11) as a time base. The phase accumulator is used to generate a set of reference waveforms (12), usually based on look-up tables and/or mathematical functions. The reference waveforms are used as the setpoint of the control loops (13) that regulate the PWM outputs (14) based on feedback from the power stages. The feedback depends on the converter type, and can be voltage and/or current measured at the power stage.
A conventional method to generate sinewaves and other periodic waveforms, usually referred as direct digital synthesis (DDS), is shown in FIG. 2. DDS is based on a look-up table (55) that stores one full period of the waveform to be synthesized, containing a number of samples exactly equal to a power of two (e.g. 210=1024). There is a phase accumulator register (53), an unsigned integer number (e.g. 32-bit), that stores the phase of the generated waveform at any given time. In order to simplify the description, the common case of 32-bit word numbers is used in the figure, but the same concept is applicable to any word size.
A value of zero in the phase accumulator generates the first sample in the waveform table, and the maximum value (e.g. 232−1) generates the last sample in the table. The phase accumulator (53) gets incremented at a fixed rate determined by an accurate clock (58), usually based on a crystal oscillator, to provide high accuracy and stability at the output frequency. At each sampling time, the output of the phase accumulator is sampled by (57) and incremented (51) by a phase delta (50). The bigger the phase delta, the faster the phase accumulator will go from 0 to its maximum value (232−1), thus determining the output frequency as:Fout=Fclock×phase_delta/232  equation (1)
Since the phase accumulator and phase delta are both 32-bit unsigned integers, their sum can be a 33-bit number in case of overflow. DDS is based on ignoring this most significant bit (MSB) (bit 33) by masking the 32 least significant bits (LSBs). When the sum exceeds the maximum 32-bit value, the phase accumulator automatically restarts a new cycle without any extra operation.
The accumulator holds the phase information in a 32-bit value, which gives high resolution and accuracy for phase and frequency, but a look-up table with 232 values would not be practical in most applications. DDS is based on a table with fewer elements, typically in the order of 1024)(210), and uses the MSBs (54) of the phase accumulator to address the corresponding table index.
The size of the table affects output distortion because each different phase value does not have a corresponding sample in the table. In high frequency applications, a low pass filter (56) can be used to successfully attenuate this effect. For low frequency output waveforms and when high accuracy is required, interpolation (56) between table values can substantially reduce distortion and mitigate the effect of a limited size table.
In certain applications the three-phase inverter topology presents important limitations, such as in the output voltage level and lack of flexibility in the possible output connections. To overcome these limitations, three separate single-phase inverters can be used to generate the three-phase output, as shown in FIG. 3. This topology employs a higher number of components, but allows full flexibility in the output connections, which is critical for some applications such as programmable AC supplies. Each single-phase inverter (27, 35, 41) generates an independent output and is controlled by a separate controller (20, 21, 22), as opposed to a single controller as FIG. 1.
State of the art technology in digital controllers allows high performance control of power converters, but the available resources can limit this performance. If a single digital controller is used to operate the three single-phase inverters of FIG. 3, the achievable performance would be significantly affected. For example, CPU (central processing unit) time is compromised when executing 3 loops in parallel, thus causing a reduction in the sampling time and consequently to the control loops bandwidth. Other limited resources are ADC modules, PWM generators, analog comparators and memory. This limitation makes necessary the use of 3 separate controllers where high performance (e.g. high accuracy, fast response) is required, such as in test and measurement applications.
In three-phase applications, the three converters of FIG. 3 need to generate the same frequency and keep an accurate phase shift of 120 degrees. Some type of mechanism must be used to synchronize the three waveform synthesizers (24, 32, 38) that runs in each controller. A conventional way of synchronizing the three controllers is shown in FIG. 3. Phase A controller (20) has a time base generator based on a phase accumulator (23), which feeds its local waveform synthesizer (24). The waveform synthesizer generates a reference to be used by the control loops and also generates a synchronization signal (28), which can be an analog signal (e.g. a sinewave) or a digital signal (e.g. a square wave). The other two controllers (21, 22) take the sync signal (28) to synchronize their local phase accumulators (31, 37) by means of a phase locked loop (PLL) (30, 36). The local time base generated by the PLLs is used by the individual waveform synthesizers (32, 38) to feed the voltage loops (33, 39). In order to provide reduced noise and ripple, the PWM generators (26, 34, 40) can also be synchronized in frequency and interleaved to switch with a predefined phase shift. This is achieved by means of a PWM sync signal (29), which is usually a digital signal of the same frequency as the PWM.
The drawback of the scheme in FIG. 3 is that the PLL, or similar synchronization circuit, has frequency and/or phase errors during transients (e.g. frequency changes). In programmable supplies for test and measurement applications, where high accuracy is required to provide consistency and repeatability, phase errors are highly undesired.
What is needed is a system with negligible phase errors between controllers.